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for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maxim integrated .com. general description the max2830 direct conversion, zero-if, rf transceiveris designed specifically for 2.4ghz to 2.5ghz 802.11g/b wlan applications. the max2830 completely integrates all circuitry required to implement the rf transceiver function, providing an rf power amplifier (pa), an rx/tx and antenna diversity switch, rf-to-baseband receive path, baseband-to-rf transmit path, voltage-controlled oscillator (vco), frequency synthesizer, crystal oscillator, and baseband/control interface. the max2830 includes a fast-settling sigma-delta rf synthesizer with smaller than 20hz frequency steps and a digitally tuned crystal oscillator allowing use of a low-cost crystal. no i/q cali- bration is required; however, the device also integrates on-chip dc-offset cancellation and i/q errors and carrier leakage-detection circuits for improved performance. only an rf bandpass filter (bpf), crystal, a pair of baluns, and a small number of passive components are needed to form a complete 802.11g/b wlan rf front- end solution. the max2830 completely eliminates the need for an external saw filter by implementing on-chip monolithic fil- ters for both the receiver and transmitter. the baseband filters are optimized to meet the ieee 802.11g standard and proprietary turbo modes up to 40mhz channel band- width. these devices are suitable for the full range of 802.11g ofdm data rates (6mbps to 54mbps) and 802.11b qpsk and cck data rates (1mbps to 11mbps). the ics are available in a small, 48-pin tqfn package measuring only 7mm x 7mm x 0.8mm. applications wi-fi, pda, voip, and cellular handsetswireless speakers and headphones general 2.4ghz ism radios features ? 2.4ghz to 2.5ghz ism band operation ? ieee 802.11g/b compatible (54mbps ofdm and 11mbps cck) ? complete rf transceiver, pa, rx/tx and antenna diversity switch, and crystal oscillator best-in-class transceiver performance 62ma receiver current 3.3db rx noise figure -75dbm rx sensitivity (54mbps ofdm) no i/q calibration required 0.1db/0.35 rx i/q gain/phase imbalance 33db rf and 62db baseband gain control range 60db range analog rssi per rf gain setting fast rx i/q dc-offset settling programmable baseband lowpass filter 20-bit sigma-delta fractional-n pll with < 20hz step size digitally tuned crystal oscillator +17.1dbm transmit power (5.6% evm with 54mbps ofdm) 31db tx gain control range integrated power detector fully integrated rf input and output matching and dc blocking serial or parallel gain-control interface > 40db tx sideband suppression without calibration rx/tx i/q error detection ? transceiver operates from +2.7v to +3.6v ? pa operates from +2.7v to +4.2v ? low-power shutdown mode ? small 48-pin tqfn package (7mm x 7mm x 0.8mm) 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch ordering information pin configuration appears at end of data sheet. par emp range pin-package max2830etm+t -40c to +85c 48 tqfn-ep* * ep = exposed paddle. + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. selector guide part integrated pa integrated switch max2830 yes yes max2831 yes no max2832 no no 19-0774; rev 2; 3/11 max2830 downloaded from: http:/// available (9$/8$7,21.,7$9$,/$%/(
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch absolute maximum ratings dc electrical characteristics (max2830 ev kit, v cc_ = 2.7v to 3.6v, v ccpa = v cctxpa = 2.7v to 4.2v, t a = -40? to +85?, rx set to the maximum gain. cs = high, rxhp = sclk = din = antsel = low, rssi and clock output buffer are off, no signal at rf inputs, all rf inputs and outputsterminated into 50 ? , receiver baseband outputs are open. 100mv rms differential i and q signals (54mbps ieee 802.11g ofdm) applied to i/q baseband inputs of transmitter in transmit mode, f ref = 40mhz, and registers set to recommended settings and corre- sponding test mode, unless otherwise noted. typical values are at v cc = 2.8v, v ccpa = 3.3v, and t a = +25?, lo frequency = 2.437ghz, unless otherwise noted. rf inputs/outputs specifications are referenced to device pins and do not include 1db loss fr om ev kit pcb, balun, and sma connectors.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cctxpa , v ccpa , and ant_ _ to gnd ..................-0.3v to +4.5v v cclna , v cctxmx , v ccpll , v cccp , v ccxtal , v ccvco , v ccrxvga , v ccrxfl , and v ccrxmx _ to gnd...-0.3v to +3.9v b6, b7, b3, b2, shdn , b5, cs , sclk, din, b1, tune, b4, antsel, txbbi_, txbbq_, rxhp, rxtx, rxbbi_, rxbbq_, rssi, bypass, cpout, ld, clockout, xtal, ctune to gnd ....................-0.3v to (operating v cc + 0.3v) rxbbi_, rxbbq_, rssi, bypass, cpout, ld, clockout short-circuit duration .........................................................10s rf input power ...............................................................+10dbm continuous power dissipation (t a = +70?) 48-pin tqfn (derates 27.8mw/? above +70?) .........2.22w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +160? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? caution! esd sensitive device parameters conditions min typ max units v cc_ 2.7 3.6 supply voltage v ccpa , v cctxpa 2.7 4.2 v s hutd own m od e, b7: b1 = 0000000, r efer ence osci ll ator not ap pl i ed t a = +25? 20 ? t a = +25? 28 35 standby mode t a = -40? to +85? 35 t a = +25? 62 78 rx mode t a = -40? to +85? 82 transmit section 82 104 tx mode, t a = +25?, v cc = 2.8v, v ccpa = 3.3v (note 2) p a, p ou t = + 17.1d bm 212 rx calibration mode t a = +25? 101 supply current tx calibration mode t a = +25? 78 ma rx i/q output common-modevoltage t a = +25? at default common-mode setting 0.94 1.2 1.37 v t a = -40? (relative to t a = +25?) -17 rx i/q output common-modevoltage variation t a = +85? (relative to t a = +25?) 15 mv tx baseband input common-mode voltage operating range dc-coupled 0.9 1.3 v tx baseband input bias current source current 22 ? 2 maxim integrated max2830 downloaded from: http:///
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch dc electrical characteristics (continued) (max2830 ev kit, v cc_ = 2.7v to 3.6v, v ccpa = v cctxpa = 2.7v to 4.2v, t a = -40? to +85?, rx set to the maximum gain. cs = high, rxhp = sclk = din = antsel = low, rssi and clock output buffer are off, no signal at rf inputs, all rf inputs and outputsterminated into 50 ? , receiver baseband outputs are open. 100mv rms differential i and q signals (54mbps ieee 802.11g ofdm) applied to i/q baseband inputs of transmitter in transmit mode, f ref = 40mhz, and registers set to recommended settings and corre- sponding test mode, unless otherwise noted. typical values are at v cc = 2.8v, v ccpa = 3.3v, and t a = +25?, lo frequency = 2.437ghz, unless otherwise noted. rf inputs/outputs specifications are referenced to device pins and do not include 1db loss fr om ev kit pcb, balun, and sma connectors.) (note 1) parameters conditions min typ max units logic inputs: shdn , rxtx, sclk, din, cs , b7:b1, rxhp, antsel digital input-voltage high, v ih v cc - 0.4 v digital input-voltage low, v il 0.4 v digital input-current high, i ih -1 +1 ? digital input-current low, i il -1 +1 ? logic outputs: ld, clockout digital output-voltage high, v oh sourcing 100? v cc - 0.4 v digital output-voltage low, v ol sinking 100? 0.4 v ac electrical characteristicsrx mode (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, t a =+25?, f rf = 2.439ghz, f lo = 2.437ghz; receiver baseband i/q out- puts at 112 mv rms (-19dbv), f ref = 40mhz, shdn = cs = high, rxtx = sclk = din = low, with power matching for the differential rf pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise note d. unmodulated single-tone rf input signal is used with specifications that normally apply over the entire operating conditions, u nless otherwise indicated. rf inputs/outputs specifications are referenced to device pins and do not include 1db loss from ev kit pcb , balun, and sma connectors.) (note 1) parameter conditions min typ max units receiver section: lna rf input-to-baseband i/q outputs rf input frequency range 2.4 2.5 ghz high rf gain 13 mid rf gain 16 rf input return loss (ant1) low rf gain 13 db high rf gain 21 mid rf gain 14 rf input return loss (ant2) low rf gain 12 db t a = +25? 86 97 maximum gain, b7:b1 =1111111 t a = -40? to +85? 83 total voltage gain (ant1) minimum gain, b7:b1 =0000000 t a = +25? 2 8 db maximum gain, b7:b1 =1111111 t a = +25? 96 total voltage gain (ant2) minimum gain, b7:b1 =0000000 t a = +25? 2 db maxim integrated 3 max2830 downloaded from: http:///
ac electrical characteristicsrx mode (continued) (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, t a =+25?, f rf = 2.439ghz, f lo = 2.437ghz; receiver baseband i/q out- puts at 112 mv rms (-19dbv), f ref = 40mhz, shdn = cs = high, rxtx = sclk = din = low, with power matching for the differential rf pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise note d. unmodulated single-tone rf input signal is used with specifications that normally apply over the entire operating conditions, u nless otherwise indicated. rf inputs/outputs specifications are referenced to device pins and do not include 1db loss from ev kit pcb , balun, and sma connectors.) (note 1) parameter conditions min typ max units from high-gain mode (b7:b6 = 11) to medium-gainmode (b7:b6 = 10) -17 rf gain steps (note 3) from high-gain mode (b7:b6 = 11) to low-gain mode(b7:b6 = 0x) -33.5 db rf gain-change settling time gain change from high gain to medium gain, high gain tolow, or medium gain to low gain; gain settling to within ?db of steady state; rxhp = 1 0.2 ? baseband gain range from maximum baseband gain (b5:b1 = 11111) to minimum baseband gain (b5:b1 = 00000) 54 62 68 db voltage gain = maximum with b7:b6 = 11 3.3 voltage gain = 50db with b7:b6 = 11 3.8 voltage gain = 45db with b7:b6 = 10 16.7 dsb noise figure (ant1) voltage gain = 15db with b7:b6 = 0x 34.7 db voltage gain = maximum with b7:b6 = 11 4.0 voltage gain = 50db with b7:b6 = 11 4.5 voltage gain = 45db with b7:b6 = 10 17.4 dsb noise figure (ant2) voltage gain = 15db with b7:b6 = 0x 35.3 db b7:b6 = 11 -41 b7:b6 = 10 -24 in-band compression pointbased on evm -19dbv rms baseband output evm degrades to9% b7:b6 = 0x -6 dbm in-band output p-1db voltage gain = 90db, with b7:b6 = 11 2.5 v p-p b7:b6 = 11 -12 b7:b6 = 10 -4 out-of-band input ip3 (note 4) b7:b6 = 0x 24 dbm i/q phase error 1 variation (without calibration) ?.35 d eg r ees i/q gain imbalance 1 variation (without calibration) ?.1 db minimum differential resistance 10 k rx i/q output load impedance(r || c) maximum differential capacitance 10 pf tx-to-rx conversion gain for rxi/q calibration for receiver gain, b7:b1 = 1101111 (note 5) 0.5 db baseband vga settling time gain change from b5:b1 = 10111 to b5:b1 = 00111; gainsettling to within ?db of steady state 0.1 ? i/q output dc step when rxhptransitions from 1 to 0 in presence of 802.11g short sequence after switching rxhp to logic 0 from initial logic 1, duringideal short sequence data at -55dbm input in awgn channel, for -19dbv output; normalized to rms signal on i and q outputs; transition point varied from 0 to 0.8? in steps of 0.1? -5 dbc 4 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch ac electrical characteristicsrx mode (continued) (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, t a =+25?, f rf = 2.439ghz, f lo = 2.437ghz; receiver baseband i/q out- puts at 112 mv rms (-19dbv), f ref = 40mhz, shdn = cs = high, rxtx = sclk = din = low, with power matching for the differential rf pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise note d. unmodulated single-tone rf input signal is used with specifications that normally apply over the entire operating conditions, u nless otherwise indicated. rf inputs/outputs specifications are referenced to device pins and do not include 1db loss from ev kit pcb , balun, and sma connectors.) (note 1) parameter conditions min typ max units i/q output dc droop after switching rxhp to 0, d13:d12, register 7(a3:a0 = 0111) ? v/s i/q static dc offset rxhp = 1, b7:b1 = 1101110, 1 variation ? mv spurious signal emissions fromlna input rf = 1ghz to 26.5ghz -51 dbm ant1 to receiver (in ant2 mode) 20 ant to receiver isolation ant2 to receiver (in ant1 mode) 47 db receiver baseband filters gain ripple in passband 10khz to 8.5mhz at baseband ?.3 db p-p g r oup - d el ay ri p p l e i n p assb and 10khz to 8.5mhz at baseband ?5 ns p-p at 8.5mhz 3.2 at 15mhz 27 at 20mhz 50 baseband filter rejection(nominal mode) at > 40mhz 80 db rssi rssi minimum output voltage r load 10k || 5pf 0.4 v rssi maximum output voltage r load 10k || 5pf 2.4 v rssi slope 30 mv/db +32db signal step 200 rssi output settling time to within 3db of steadystate -32db signal step 600 ns maxim integrated 5 max2830 downloaded from: http:///
ac electrical characteristicstx mode (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, t a = +25?, f rf = 2.439ghz , f lo = 2.437ghz. f ref = 40mhz, shdn = rxtx = cs = antsel = high, and sclk = din = low, with power matching for the differential rf pins using the typical applications circuit. 100mv rms sine and cosine signal (or 100mv rms 54mbps ieee 802.11g i/q signals wherever ofdm is mentioned) applied to baseband i/q inputs of transmitter (differential dc-coupled). registers set to recommend settings and corresponding test mode,unless otherwise noted. rf inputs/outputs specifications are referenced to device pins and do not include 1db loss from ev kit pcb, balun, and sma connectors.) (note 1) parameter conditions min typ max units transmit section: tx baseband i/q inputs to rf outputs rf output frequency range 2.4 2.5 ghz 54mbps 802.11g ofdmsignal output power adjusted tomeet 5.6%evm, and spectral mask 17.1 output power 6mbits, ofdm, i/q signals output power adjusted tomeet spectral mask 20.3 dbm gain control range b6:b1 = 000000 to 111000 26 db unwanted sideband suppression without i/q calibration, b6:b1 = 100001 -42 dbc carrier leakage at centerfrequency of channel without dc offset correction -30 dbc 1/3 x f lo -67 < 1ghz -36 > 1ghz -47 2/3 x f lo -64 4/3 x f lo -42 5/3 x f lo -65 8/3 x f lo -55 2 x f lo -27 transmitter spurious signalemissions b6:b1 = 111000,ofdm signal 3 x f lo -54 dbm/ mhz rf output return loss o ff- chi p b al un and si ng l e end ed -15 db minimum differential resistance 20 k tx i/q input load impedance(r || c) maximum differential capacitance 0.7 pf baseband -3db cornerfrequency d1:d0 = 01, register 8(a3:a0 = 1000) nominal mode 11 mhz baseband filter rejection at 30mhz, in nominal mode 62 db minimum power-detector outputvoltage short sequence transmitter power = +10dbm 0.35 v maximum power-detector outputvoltage short sequence transmitter power = +20dbm 1.2 v rf p ow er - d etector resp onse ti m e 0.3 ? 6 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch ac electrical characteristicstx mode (continued) (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, t a = +25?, f rf = 2.439ghz , f lo = 2.437ghz. f ref = 40mhz, shdn = rxtx = cs = antsel = high, and sclk = din = low, with power matching for the differential rf pins using the typical applications circuit. 100mv rms sine and cosine signal (or 100mv rms 54mbps ieee 802.11g i/q signals wherever ofdm is mentioned) applied to baseband i/q inputs of transmitter (differential dc-coupled). registers set to recommend settings and corresponding test mode,unless otherwise noted. rf inputs/outputs specifications are referenced to device pins and do not include 1db loss from ev kit pcb, balun, and sma connectors.) (note 1) parameter conditions min typ max units transmitter lo leakage and i/q calibration using lo leakage and sideband detector (see the rx/tx calibration mode section) tx baseband i/q inputs to receiver outputs output at 1 x f tone (for lo leakage = -29dbc),f tone = 2mhz, 100mv rms -34 lo leakage and sidebanddetector output calibration register,d12:d11 = 00, a3:a0 = 0110 output at 2 x f tone (for lo leakage = -240dbc),f tone = 2mhz, 100mv rms -44 dbv rms amplifier gain range d12:d11 = 00 to d12:d11 = 11, a3:a0 = 0110 30 db lower -3db corner frequency 1 mhz maxim integrated 7 max2830 downloaded from: http:///
ac electrical characteristicsfrequency synthesizer (max2830 ev kit, v cc_ = 2.7v, v ccpa = v cctxpa = 3.3v, t a = +25?, f lo = 2.437ghz, f ref = 40mhz, shdn = cs = high, sclk = din = low, pll loop bandwidth = 150khz, and t a = +25?, unless otherwise noted.) (note 1) parameter conditions min typ max units frequency synthesizer rf channel center frequency 2.4 2.5 ghz channel center frequencyprogramming minimum step size 20 hz charge-pump comparisonfrequency 20 mhz reference frequency range 20 44 mhz reference frequency inputlevels ac-coupled to xtal pin 800 mv p-p resistance (xtal) 5 k reference frequency inputimpedance (r || c) capacitance (xtal) 4 pf f offset = 1khz -86 f offset = 10khz -94 f offset = 100khz -94 f offset = 1mhz -110 closed-loop phase noise f offset = 10mhz -120 dbc/hz closed-loop integrated phasenoise rms phase jitter; integrate from 10khz to 10mhz offset 0.9 d eg r ees charge-pump output current 1m a reference spurs 20mhz offset -55 dbc 3? to 9? 50 vco frequency error m easur ed fr om tx- rx or rx- tx tr ansi ti on > 9? 1 khz voltage-controlled oscillator pushing referred to 2400mhz lo, v cc varies by 0.3v 210 khz v tune = 0.5v 103 lo tuning gain v tune = 2.2v 86 mhz/v 8 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch ac electrical characteristicsmiscellaneous blocks (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, f lo = 2.437ghz, f ref = 40mhz, shdn = cs = high, sclk = din = low, and t a = +25?, unless otherwise noted.) (note 1) parameter conditions min typ max units crystal oscillator m axi m um cap aci tance, a3:a0 = 1110, d 6:d 0 = 1111111 15.4 on-chip tuning capacitancerange m i ni m um cap aci tance, a3:a0 = 1110, d 6:d 0 = 0000000 0.5 pf on-chip tuning capacitancestep size 0.12 pf on-chip temperature sensor t a = -40? 0.35 t a = +25? 1 output voltage a3:a0 = 1000, d 9:d 8 = 01 t a = +85? 1.6 v ac electrical characteristicstiming (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, t a =+25?, f lo = 2.437ghz, f ref = 40mhz, shdn = cs = high, sclk = din = low, pll loop bandwidth = 150khz, and t a = +25?, unless otherwise noted.) (note 1) parameter conditions min typ max units system timing (see figure 3) turn-on time from shdn rising edge to lo settled within 1khz using external reference frequency input 60 ? crystal oscillator turn-on time 90% of final output amplitude level 1 ms channel switching time loop bw = 150khz, f rf = 2.5ghz to 2.4ghz 25 ? rx to tx 2 rx/tx turnaround time measured from tx or rx enable rising edge; signal settling to within ?db of steady state tx to rx, rxhp = 1 2 ? tx turn-on time (from standbymode) from tx-enable active rising edge; signal settling to within ?db of steady state 1.5 ? tx turn-off time (from standbymode) from tx-enable inactive rising edge 1 ? rx turn-on time (from standbymode) from rx-enable active rising edge; signal settling towithin ?db of steady state 1.9 ? rx turn-off time (from standbymode) from rx-enable inactive rising edge 0.1 ? maxim integrated 9 max2830 downloaded from: http:///
ac electrical characteristicstiming (continued) (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, t a =+25?, f lo = 2.437ghz, f ref = 40mhz, shdn = cs = high, sclk = din = low, pll loop bandwidth = 150khz, and t a = +25?, unless otherwise noted.) (note 1) parameter conditions min typ max units 3-wire serial-interface timing (see figure 2) sclk rising edge to cs falling edge wait time, t cso 6n s falling edge of cs to rising edge of first sclk time, t css 6n s din to sclk setup time, t ds 6n s din to sclk hold time, t dh 6n s sclk pulse-width high, t ch 6n s sclk pulse-width low, t cl 6n s last rising edge of sclk torising edge of cs or clock to load enable setup time, t csh 6n s cs high pulse width, t csw 20 ns time between the rising edge ofcs and the next rising edge of sclk, t cs1 6n s clock frequency, f clk 20 mhz rise time, t r 2n s fall time, t f 2n s note 1: min and max limits are guaranteed by test above t a = +25? and guaranteed by design and characterization at t a = -40?. the power-on register settings are not production tested. recommended register setting must be loaded after v cc is supplied. note 2: guaranteed by design and characterization. note 3: the nominal part-to-part variation of the rf gain step is ?db. note 4: two tones at +25mhz and +48mhz offset with -35dbm/tone. measure im3 at 2mhz. note 5: tx i/q inputs = 100mv rms . 10 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch rx i cc vs. v cc v cc (v) i cc (ma) max2830 toc01 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 61 62 63 64 65 66 67 t a = +25 c t a = -40 c t a = +85 c noise figure vs. baseband gain settings gain settings nf (db) max2830 toc02 02468101214161820222426283032 0 5 10 15 20 25 30 35 40 45 lna = high gain lna = medium gain lna = low gain rx voltage gain vs. baseband gain setting gain settings gain (db) max2830 toc03 02468101214161820222426283032 0 10 20 30 40 50 60 70 80 90 100 lna = low gain lna = medium gain lna = high gain rx in-band output p - 1db vs. gain gain (db) output p - 1db (dbv rms ) max2830 toc04 15 25 35 45 55 65 75 85 95 -7 -6 -5 -4 -3 -2 -1 0 lna medium/high- gain switch point lna medium/low- gain switch point rx evm vs. p in p in (dbm) evm (%) max2830 toc05 -80 -70 -60 -50 -40 -30 -20 -10 0 0 2 4 6 8 10 12 14 16 18 20 22 lna = high gain lna = low gain lna = medium gain rx evm vs. v out v out (dbv rms ) evm (%) max2830 toc06 -29 -27 -25 -23 -21 -19 -17 -15 -13 -11 -9 0 0.5 1.0 1.5 2.0 2.5 3.0 p in = -50dbm lna = high gain ofdm evm with ofdm jammer vs. offset frequency p jammer (dbm) evm (%) max2830 toc07 -65 -55 -45 -35 -25 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 f offset = 20mhz f offset = 25mhz f offset = 40mhz p in = -62dbm rx emission spectrum, lna input max2830 toc08 4/3 lo 2 lo 8/3 lo 4 lo 16/3 lo 20/3 lo dbm -50-60 -70 -80 -90 -100-110 -120 -130 -140 -150 dc 26.5ghz lna input return loss vs. rf frequency (ant 1) rf frequency (mhz) input return loss (db) max2830 toc09 2300 2400 2500 2600 -25 -20 -15 -10 -5 mid gain low gain high gain typical operating characteristics (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, t a = +25?, f lo = 2.437ghz, f ref = 40mhz, shdn = cs = high, rxhp = sclk = din = low.) maxim integrated 11 max2830 downloaded from: http:///
typical operating characteristics (continued) (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, t a = +25?, f lo = 2.437ghz, f ref = 40mhz, shdn = cs = high, rxhp = sclk = din = low.) lna input return loss vs. rf frequency (ant 2) rf frequency (mhz) input return loss (db) max2830 toc09a 2300 2400 2500 2350 2450 2550 2600 -25 -20 -15 -10 -5 mid gain low gain high gain rx rssi output vs. input power p in (dbm) rssi output (v) max2830 toc10 -120 -100 -80 -60 -40 -20 0 20 0 0.5 1.0 1.5 2.0 2.5 3.0 lna = high gain lna = medium gain lna = low gain rx rssi step response (+32db lna gain step) 3v 0 0.45 1.45v 200ns/div max2830 toc11 rx rssi step response (-32db lna gain step) 3v0v 0v 1.5v 200ns/div max2830 toc12 rx i/q dc offset settling response (+8db bb vga gain step) 2.0v 5mv 40ns/div 10mv 0v0v max2830 toc13 rx i/q dc offset settling response (-8db bb vga gain step) max2830 toc14 2.5v 5mv 40ns/div 10mv 0v 0mv rx i/q dc offset settling response (-16db bb vga gain step) 3v max2830 toc15 5mv 400ns/div 10mv 0v0v rx i/q dc offset settling response (-32db bb vga gain step) 3v max2830 toc16 5mv 400ns/div 10mv 0v0v i/q output dc error droop (rxhp = 1 0; 100hz mode) 3v max2830 toc17 -5mv 20ms/div 0v 0v -10mv 12 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch rx bb vga settling response (+8 gain step) 500mv -500mv 3v0v 0v max2830 toc18 40ns/div rx bb vga settling response (-8 gain step) 3v0v max2830 toc19 500mv -500mv 0v 40ns/div rx bb vga settling response (-16 gain step) max2830 toc20 500mv -500mv 3v0v 0v 40ns/div rx bb vga settling response (-32 gain step) max2830 toc21 500mv -500mv 3v0v 0v 40ns/div rf lna settling response (high to medium) max2830 toc22 500mv -500mv 3v0v 0v 100ns/div rf lna settling response (high to low) max2830 toc23 500mv -500mv 3v0v 0v 100ns/div rx bb frequency response vs. fine setting (coarse setting = 8.5mhz ) frequency (mhz) db max2830 toc24 -100 -80 -60 -40 -20 0 20 1 10 100 rx bb frequency response vs. coarse setting (fine setting = 010) frequency (mhz) db max2830 toc25 -120 -100 -80 -60 -40 -20 0 20 11 01 0 0 rx baseband filter group delay max2830 toc26 frequency (mhz) 20ns/div 12 1 typical operating characteristics (continued) (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, t a = +25?, f lo = 2.437ghz, f ref = 40mhz, shdn = cs = high, rxhp = sclk = din = low.) maxim integrated 13 max2830 downloaded from: http:///
0 3819 7657 95 114 histogram: rx phase imbalance max2830 toc29 1 /div mean: 0.3 std: 0.314 sample size: 1013 tx i cc vs. v cc v cc (v) i cc (ma) max2830 toc30 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 78 80 82 84 86 88 t a = +25 c t a = -40 c t a = +85 c 0 16 8 3224 40 48 histogram: tx lo leakage max2830 toc31 1 /div mean: -33.45dbcstd: 6.31db sample size: 999 0 2613 5239 65 78 histogram: rx static dc offset max2830 toc27 1 /div mean: 0mvstd: 0.977mv sample size: 1006 0 4623 9269 115 138 histogram: rx gain imbalance max2830 toc28 1 /div mean: 0dbstd: 0.064db sample size: 951 0 2412 4836 60 72 histogram: tx sideband suppression max2830 toc32 1 /div mean: -42dbcstd: 1.9db sample size: 1000 -90 -70 -60 -50 -40 -30 -20 -10 0 0.1 1 10 100 tx baseband filter response max2830 toc33 baseband frequency (mhz) filter response (db) -80 tx evm vs. p out p out (dbm) evm (%) max2830 toc34 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 18 v cc = 4.2v v cc = 3.3v v cc = 3v v cc = 2.7v typical operating characteristics (continued) (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, t a = +25?, f lo = 2.437ghz, f ref = 40mhz, shdn = cs = high, rxhp = sclk = din = low.) pa supply current vs. p out p out (dbm) pa supply current (ma) max2830 toc35 0 5 10 15 20 25 120 150 180 210 240 270 300 330 360 v ccpa = 4.2v v ccpa = 2.7v, 3.0v, 3.3v 14 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
power detector over frequency p out (dbm) power detector (v) max2830 toc40 0 5 10 15 20 25 0 0.5 1.0 1.5 2.0 2.5 f rf = 2.4ghz f rf = 2.5ghz power detector over supply voltage p out (dbm) power detector (v) max2830 toc41 0 5 10 15 20 25 0 0.5 1.0 1.5 2.0 v ccpa = 2.7v, 3.0v v ccpa = 3.3v, 4.2v power detector over temperature p out (dbm) power detector (v) max2830 toc42 0 5 10 15 20 25 0 0.5 1.0 1.5 2.0 2.5 t a = +85 c t a = +25 c, -40 c power-detector output 100ns/div max2830 toc43 300mv -300mv 0v 1v 20db gain step pa envelope power detector 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch transmit emission mask max2830 toc38 frequency/mhz 10db/div 2467 2447 2407 2427 2387 2487 p out = +17.1dbm evm = 5.6% 802.11g p out vs. gain setting (upper gain control range) gain settings p out (dbm) max2830 toc39 40 44 48 52 56 60 64 14 16 18 20 22 typical operating characteristics (continued) (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, t a = +25?, f lo = 2.437ghz, f ref = 40mhz, shdn = cs = high, rxhp = sclk = din = low.) tx gain variation vs. frequency (b6:b1 = 101001) frequency (ghz) 2db/div max2830 toc36 2.4 2.42 2.44 2.46 2.48 2.5 t a = -40 c t a = +25 c t a = +85 c pa output envelope response 1 s/div max2830 toc44 -20dbm 0 20dbm -50mv 50mv pa envelope tx i/q input tx output power vs. frequency frequency (ghz) p out (dbm) max2830 toc37 2.40 2.42 2.44 2.46 2.48 2.50 15.0 15.5 16.0 16.5 17.0 17.5 18.0 t a = -40 c t a = +25 c t a = +85 c gain adjusted to achieve 5.6% evm maxim integrated 15 max2830 downloaded from: http:///
pa output return loss vs. rf frequency rf frequency (mhz) output return loss (db) max2830 toc45 2300 2350 2400 2450 2500 2550 2600 -20 -18 -16 -14 -12 -10 tx output spurs max2830 toc46 0 -80-90 10 -70 -60 -50 -40 -30 -20 -10 26.5ghz dc lo 2x lo 3x rf rbw = 1mhz 802.11g signal 43 lo 83 lo pll settling time from shutdown to standby mode 50khz -50khz 0 2ms 10khz/ div max2830 toc50 channel switching frequency settling (from 2500mhz to 2400mhz) 50khz -50khz 250 s 0 10khz/ div max2830 toc49 lo phase noise vs. offset frequency offset frequency (mhz) phase noise (dbc/hz) max2830 toc48 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 0.001 0.01 0.1 1 10 lo frequency vs. v tune v tune (v) lo frequency (mhz) max2830 toc47 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2300 2350 2400 2450 2500 2550 2600 typical operating characteristics (continued) (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, t a = +25?, f lo = 2.437ghz, f ref = 40mhz, shdn = cs = high, rxhp = sclk = din = low.) pll settling time from standby to tx 50khz -50khz 03 0 s 10khz/ div max2830 toc51 16 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch rx-to-tx turnaround pll settling time 25khz -25khz 50 s 0 5khz/ div max2830 toc52 tx-rx turnaround pll settling time 5khz/div -25khz 05 0 s 25khz max2830 toc53 typical operating characteristics (continued) (max2830 ev kit, v cc_ = 2.8v, v ccpa = v cctxpa = 3.3v, t a = +25?, f lo = 2.437ghz, f ref = 40mhz, shdn = cs = high, rxhp = sclk = din = low.) clock output 0v 10ns/div 3v max2830 toc54 f clock = 40mhz c load = 5pf crystal-oscillator offset frequency vs. crystal-oscillator tuning bits c tune (digital bits) crystal offset frequency (hz) max2830 toc55 0 102030405060708090100110120130 -800 -700 -600 -500 -400 -300 -200 -100 0 100 200 300 400 500 600 700 800 kyocera (cx-3225sb) maxim integrated 17 max2830 downloaded from: http:///
b2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v cclna b6 gndrxlna ant1+ ant1- b7 v ccpa ant2+ ant2- shdn power detector serial interface temp sensor am detector v cctxpa b5 cs rssi v cctxmx sclk din v ccpll clockout ld b1 cpout rxbbq+rxbbq- rx qoutputs rx/tx gain control b4 bypass tune gndvco ctune v ccvco xtal pll %1,2 %1,2 gndcp serial inputs v ccxtal v cccp rxtx antsel v ccrxmx txbbi+ txbbi- txbbq+ txbbq- v ccrxfl rxhp v ccrxvga rxbbi+ rxbbi- max2830 mode control rx/tx gain control rx/tx gain control reference clock buffer output note: all ground pins (pins 2, 26, and 31) and bypass capacitors? ground require their own vias to ground. do not connect them to the exposed paddle ground. rx baseband hpf corner frequency control b3 rx/tx gain control rx input tx output mode control rx/tx gain control rx/tx gain control rx gain control tx input rx i outputs 0 90 rssi mux to rssimux rssi temp sensor crystal oscillator/ buffer rssi torssi mux mux imux qmux mux rx/tx antenna switch block diagram/typical operating circuit 18 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
pin description pin name function 1v cclna lna supply voltage 2g n drx lna lna ground 3 b6 receiver and transmitter gain-control logic-input bit 6 4 ant1+ 5 ant1- antenna 1. differential input to lna in rx mode. input is internally ac-coupled and matched to 100 differential. connect directly to a 2:1 balun. 6 b7 receiver gain-control logic-input bit 7 7v ccpa supply voltage for second stage of power amplifier 8 b3 receiver and transmitter gain-control logic-input bit 3 9 ant2+ 10 ant2- antenna 2. differential inputs to lna in diversity rx mode and to pa differential outputs in tx mode. internally ac-coupled differential outputs and matched to 100 differential. connect directly to a 2:1 balun. 11 b2 receiver and transmitter gain-control logic-input bit 2 12 shdn active-low shutdown and standby logic input. see table 32 for operating modes. 13 v cctxpa supply voltage for first-stage of pa and pa driver 14 b5 receiver and transmitter gain-control logic-input bit 5 15 cs active-low chip-select logic input of 3-wire serial interface (see figure 3) 16 rssi rssi, pa power detector or temperature-sensor multiplexed analog output 17 v cctxmx transmitter upconverter supply voltage 18 sclk serial-clock logic input of 3-wire serial interface (see figure 3) 19 din data logic input of 3-wire serial interface (see figure 3) 20 v ccpll pll and registers supply voltage. connect to the supply voltage to retain the register settings. 21 clockout reference clock buffer output 22 ld lock- d etect log i c outp ut of fr eq uency s ynthesi zer . o utp ut hi g h i nd i cates that the fr eq uency synthesi zer i s l ocked . outp ut p r og r am m ab l e as c m o s or op en- d r ai n outp ut. ( s ee tab l es 17 and 21.) 23 b1 receiver and transmitter gain-control logic-input bit 1 24 cpout charge-pump output. connect the frequency synthesizer? loop filter between cpout and tune (see the block diagram/typical operating circuit ). 25 v cccp pll charge-pump supply voltage 26 gndcp charge-pump circuit ground 27 v ccxtal crystal oscillator supply voltage 28 xtal crystal or reference clock input. ac-couple a crystal or a reference clock to this analog input. 29 ctune connection for crystal oscillator off-chip capacitors. when using an external reference clock input, leavectune unconnected. 30 v ccvco vco supply voltage 31 gndvco vco ground 32 tune vco tune input (see the block diagram/typical operating circuit ) 33 bypass on-chip vco regulator output bypass. bypass with a 0.1? to 1? capacitor to gnd. do not connect other circuitry to this point. 34 b4 receiver and transmitter gain-control logic-input bit 4 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch maxim integrated 19 max2830 downloaded from: http:///
detailed description the max2830 single-chip, low-power, direct conversion,zero-if transceiver is designed to support 802.11g/b applications operating in the 2.4ghz to 2.5ghz band. the fully integrated transceivers include a receive path, transmit path, vco, sigma-delta fractional-n synthesizer, crystal oscillator, rssi, pa power detector, temperature sensor, rx and tx i/q error-detection circuitry, baseband- control interface, linear power amplifier, and an rx/tx antenna diversity switch. the only additional components required to implement a complete radio front-end solution are a crystal, a pair of baluns, a bpf, and a small number of passive components (rcs, no inductors required). rx/tx and antenna diversity switches the max2830 integrates an rx/tx switch and an anten- na diversity switch before the receiver and after the power amplifier. see figure 1 for a block diagram of the switches. the receiver and transmitter enable pin (rxtx) and the antenna selection pin (antsel) deter- mine which ports (ant1 or ant2) the receiver or trans- mitter is connected to. see table 1 for the rx/tx and antenna diversity switches truth table. when rxtx = 0 (receive mode) and antsel = 0, the switch provides alow-insertion loss path (main) between the ant1 port (pins 4 and 5) and the receiver. when rxtx = 0 (receive mode) and antsel = 1, the switch provides pin description (continued) pin name function 35 rxbbq- 36 rxbbq+ receiver baseband q-channel differential outputs. in tx calibration mode, these pins are the lo leakageand sideband detector outputs. 37 rxbbi- 38 rxbbi+ receiver baseband i-channel differential outputs. in tx calibration mode, these pins are the lo leakageand sideband detector outputs. 39 v ccrxvga receiver vga supply voltage 40 rxhp receiver baseband ac-coupling high-pass corner frequency control logic input 41 v ccrxfl receiver baseband filter supply voltage 42 txbbq- 43 txbbq+ transmitter baseband i-channel differential inputs 44 txbbi- 45 txbbi+ transmitter baseband q-channel differential inputs 46 v ccrxmx receiver downconverters supply voltage 47 antsel antenna selection logic input. see table 1 for operation 48 rxtx rx/tx mode control logic input. see table 32 for operating modes. ? p exposed paddle. connect to the ground plane with multiple vias for proper operation and heat dissipation. do not share with any other pin grounds and bypass capacitors' ground. table 1. rx/tx and antenna diversity switches operation rxtx antsel mode antenna 0 0 rx (main) ant1_ 0 1 rx (diversity) ant2_ 1 x tx ant2_ max2830 2 2 ant1 2 2 lna pa 2 ant2 figure 1. simplified rx/tx and antenna diversity switch structure 20 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch an antenna diversity path between the ant2 port (pins9 and 10) and the receiver. when rxtx = 1, the pa and transmit path are automatically connected to the ant2 port, regardless of the logic state of antsel. for solutions not requiring antenna diversity, set antsel logic-level high, enabling only the ant2 port for both receive and transmit modes. the ant1 and ant2 differential ports are internally ac- coupled and internally matched to 100 ? . directly con- nect 2:1 baluns or balanced bandpass filters (bpfs) tothese ports for applications requiring antenna diversity. for applications not requiring antenna diversity, only a single balun or balanced bpf is required on the ant2 port, and the ant1 port can be left open. provide elec- trically symmetrical input traces to the baluns to main- tain ip2 and rf common-mode noise rejection for the receiver, and to maintain a balanced load for the pa. receiver after the switch, the receiver integrates an lna and vgawith a 95db digitally programmable gain control range, direct-conversion downconverters, i/q baseband low- pass filters with programmable lpf corner frequencies, analog rssi and integrated dc-offset correction circuitry. a logic-low on the rxtx input (pin 48) and a logic-high on the shdn input (pin 12) enable the receiver. lna gain control the lna has three gain modes: max gain, max gain -16db, and max gain -33db. the three lna gain modes can be serially programmed through the spi interface by programming bits d6:d5 in register 11(a3:a0 = 1011) or programmed in parallel through the digital logic gain-control pins, b7 (pin 6) and b6 (pin 3). set bit d12 = 1 in register 8 (a3:a0 = 1000) to enable programming through the spi interface, or set bit d12 = 0 to enable parallel programming. see table 2 for lna gain-control settings. baseband variable-gain amplifier the receiver baseband variable-gain amplifiers provide62db of gain control range programmable in 2db steps. the vga gain can be serially programmed through the spi interface by setting bits d4:d0 in register 11 (a3:a0 = 1011) or programmed in parallel through the digital logic gain-control pins, b5 (pin 14), b4 (pin 34), b3 (pin 8), b2 (pin 11), and b1 (pin 23). set bit d12 = 1 in register 8 (a3:a0 = 1000) to enable serial programming through the serial interface or set bit d12 = 0 to enable parallel programming through the external logic pins. see table 3 for the gain-step value and table 4 for baseband vga gain-control settings. receiver baseband lowpass filter the receiver integrates lowpass filters that provide anupper -3db corner frequency of 8.5mhz (nominal mode) with 50db of attenuation at 20mhz, and 45ns of group delay ripple in the passband (10khz to 8.5mhz). the upper -3db corner frequency is tightly controlled on-chip and does not require user adjustment. however, provi- sions are made to allow fine tuning of the upper -3db table 3. receiver baseband vga gain- step value (pins b5:b1 or register d4:d0, a3:a0 = 1011) table 4. baseband vga gain-control settings in receiver gain-control register (pin b5:b1 or register d4:d0, a3:a0 = 1011) table 5. receiver lpf coarse -3db corner frequency settings in register (a3:a0 = 1000) pin/bit gain step (db) b1/d0 2 b2/d1 4 b3/d2 8 b4/d3 16 b5/d4 32 b5:b1 or d4:d0 gain 11111 max 11110 max - 2db 11101 max - 4db :: 00000 min bits (d1:d0) -3db corner frequency (mhz) mode 00 7.5 11b 01 8.5 11g 10 15 turbo 1 11 18 turbo 2 table 2. lna gain-control settings (pins b7:b6 or register a3:a0 = 1011, d6:d5) b7 or d6 b6 or d5 name description 1 1 high max gain 1 0 medium max gain - 16db (typ) 0 x low max gain - 33db (typ) spi is a trademark of motorola, inc. maxim integrated 21 max2830 downloaded from: http:///
corner frequency. in addition, coarse frequency tuningallows the -3db corner frequency to be set to 7.5mhz (11b mode), 8.5mhz (11g mode), 15mhz (turbo 1 mode), and 18mhz (turbo 2 mode) by programming bits d1:d0 in register 8 (a3:a0 = 1000). see table 3. the coarse corner frequency can be fine-tuned approximately ?0% in 5% steps by programming bits d2:d0 in register 7 (a3:a0 = 0111). see table 6 for receiver lpf fine -3db corner frequency adjustment. baseband highpass filter and dc offset correction the receiver implements programmable ac and near-dc coupling of i/q baseband signals. temporary ac- coupling is used to quickly remove lo leakage and other dc offsets that could saturate the receiver out- puts. when dc offsets have settled, near dc-coupling is enabled to avoid attenuation of the received signal. ac-coupling is set (-3db highpass corner frequency of 600khz) when a logic-high is applied to rxhp (pin 40). near dc-coupling is set (-3db highpass corner fre- quency of 100hz nominal) when a logic-low is applied to rxhp. bits d13:d12 in register 7 (a3:a0 = 0111) allow the near dc-coupling -3b highpass corner fre- quency to be set to 100hz (d13:d12 = 00), 4khz (d13:d12 = x1), or 30khz (d13:d12 = 10). see table 7. receiver i/q baseband outputs the differential outputs (rxbbi+, rxbbi-, rxbbq+,rxbbq-) of the baseband amplifiers have a differential output impedance of ~300 ? , and are capable of dri- ving differential loads up to 10k ? || 10pf. the outputs are internally biased to a common-mode voltage of1.2v and are intended to be dc-coupled to the in- phase (i) and quadrature (q) analog-to-digital data converter inputs of the accompanying baseband ic. additionally, the common-mode output voltage can be adjusted from 1.2v to 1.5v through programming bits d11:d10 in register 15 (a3:a0 = 1111). received signal-strength indicator (rssi) the rssi output (pin 16) can be programmed to multi-plex an analog output voltage proportional to the received signal strength, the pa output power, or the die temperature. set bits d9:d8 = 00 in register 8 (a3:a0 = 1000) to enable the rssi output in receive mode (off in transmit mode). set bit d10 = 1 to enable the rssi output when rxhp = 1, and disable the rssi output when rxhp = 0. set bit d10 = 0 to enable the rssi output independent of rxhp. see table 8 for a summary of the rssi output vs. register programming and rxhp. the rssi provides an analog voltage proportional to the log of the sum of the squares of the i and q chan- nels, measured after the receive baseband filters and before the variable-gain amplifiers. the rssi analog output voltage is proportional to the rf input signal level and lna gain state over a 60db range, and is not dependent upon vga gain. see the rx rssi output vs. input power graph in the typical operating characteristics for further details. table 8. rssi pin truth table input conditions a3:a0 = 1000, d9:d8 a3:a0 = 1000, d10 rxhp rssi output x 0 0 no signal 00 0 1 rssi 01 0 1 temperature sensor 10 0 1 power detector 00 1 x rssi 01 1 x temperature sensor 10 1 x power detector table 6. receiver lpf fine -3db corner frequency adjustment in register (a3:a0 = 0111) bits (d2:d0) % adjustment relative to coarse setting 000 90 001 95 010 100 011 105 100 110 table 7. receiver highpass filter -3db corner frequency programming rxhp a3:a0 = 0111, d13:d12 -3db highpass corner frequency (hz) 1 xx 600k 0 00 100 (recommended) 0x 1 4 k 0 10 30k x = don? care. x = don? care. 22 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch transmitter the transmitter integrates baseband lowpass filters,direct-upconversion mixers, a vga, a pa driver, and a lin- ear rf pa with a power detector. a logic-high on the rxtx input (pin 48) and a logic-high on the shdn input (pin 12) enable the transmitter. the pa outputs are routedto ant2, regardless of the state at antsel. transmitter i/q baseband inputs the differential analog inputs of the transmitter basebandamplifier i/q inputs (txbbi+, txbbi-, txbbq+, txbbq-) have a differential impedance of 20k ? || 1pf. the inputs require an input common-mode voltage of 0.9v to 1.3v,which is provided by the dc-coupled i and q dac out- puts of the accompanying baseband ic. transmitter baseband lowpass filtering the transmitter integrates lowpass filters that can betuned to -3db corner frequencies of 8mhz (11b), 11mhz (11g), 16.5mhz (turbo 1 mode), and 22.5mhz (turbo 2 mode) through programming bits d1:d0 in register 8 (a3:a0 = 1000) and bit d5:d3 in register 7(a3:a0 = 0111). the -3db corner frequency is tightly controlled on-chip and does not require user adjust- ment. additionally, provisions are made to fine tune the -3db corner frequency through bits d5:d3 in the filter programming register (a3:a0 = 0111). see tables 9 and 10. transmitter variable-gain amplifier the variable-gain amplifier of the transmitter provides31db of gain control range programmable in 0.5db steps over the top 8db of the gain control range and in 1db steps below that. the transmitter gain can be pro- grammed serially through the spi interface by setting bits d5:d0 in register 12 (a3:a0 = 1100) or in parallel through the digital logic gain-control pins b6:b1 (pins 3, 6, 8, 11, 14, 23, and 34, respectively). set bit d10 = 0 in register 9 (a3:a0 = 1001) to enable parallel pro- gramming, and set bit d10 = 1 to enable programming through the 3-wire serial interface. see table 11 for the transmitter vga gain-control settings. table 11. transmitter vga gain-control settings no. d5:d0 or b6:b1 output signal power 63 111111 max 62 111110 max - 0.5db 61 111101 max - 1.0db :: : 49 110001 max - 7db 48 110000 max - 7.5db 47 101111 max - 8db 46 101110 max - 8db 45 101101 max - 9db 44 101100 max - 9db :: : 5 000101 max - 29db 4 000100 max - 29db 3 000011 max - 30db 2 000010 max - 30db 1 000001 max - 31db 0 000000 max - 31db table 9. transmitter lpf coarse -3db corner frequency settings in register (a3:a0 = 1000) bits (d1:d0) -3db corner frequency (mhz) mode 00 8 11b 01 11 11g 10 16.5 turbo 1 11 22.5 turbo 2 table 10. transmitter lpf fine -3db corner frequency adjustment in register (a3:a0 = 0111) bits (d5:d3) % adjustment relative to coarse setting 000 90 001 95 010 100 011 105 100 110 (11g) 101 115 101?11 not used maxim integrated 23 max2830 downloaded from: http:///
power-amplifier bias and enable delay the max2830 integrates a 2-stage pa, providing+17.1dbm of output power at 5.6% error vector magni- tude (evm) (54mbps ofdm signal) in 802.11g mode while exceeding the 802.11g spectral mask require- ments. the first and second stage pa bias currents are set through programming bits d2:d0 and bits d6:d3 in register 10 (a3:a0 = 1010), respectively. an adjustable pa enable delay, relative to the transmitter enable (rxtx low-to-high transition), can be set from 200ns to 7? through programming bits d13:d10 in register 10 (a3:a0 = 1010). power detector the max2830 integrates a voltage-peak detector at thepa output and before the switch to provide an analog voltage proportional to pa output power. see the power detector over frequency and power detector over supply voltage graphs in the typical operating characteristics . set bits d9:d8 = 10 in register 8 (a3:a0 = 1000) to multiplex the power-detector analog outputvoltage to the rssi output (pin 16). synthesizer programming the max2830 integrates a 20-bit sigma-delta fractional-n synthesizer, allowing the device to achieve excellent phase-noise performance (0.9 rms from 10khz to 10mhz), fast pll settling times, and an rf frequency step-size of 20hz. the synthesizer includes a divide-by- 1 or a divide-by-2 reference frequency divider, an 8-bitinteger portion main divider with a divisor range pro- grammable from 64 to 255, and a 20-bit fractional por- tion main-divider. bit d2 in register 5 (a3:a0 = 0101) sets the reference oscillator divider ratio to 1 or 2. bits d7:d0 in register 3 (a3:a0 = 0011) set the integer por- tion of the main divider. the 20-bit fractional portion of the main-divider is split between two registers. the 14 msbs of the fractional portion are set in register 4 (a3:a0 = 0100), and the 6 lsbs of the fractional portion of the main divider are set in register 3 (a3:a0 = 0011). see tables 12 and 13. calculating integer and fractional divider ratios the desired integer and fractional divider ratios can becalculated by dividing the rf frequency (f rf ) by f comp . for nominal 802.11g/b operation, a 40mhz referenceoscillator is divided by 2 to generate a 20mhz compari- son frequency (f comp ). the following method can be used when calculating divider ratios supporting variousreference and comparison frequencies: lo frequency divider = f rf / f comp = 2437mhz / 20mhz = 121.85 integer divider = 121 (d) = 0111 1001 (binary) fractional divider = 0.85 x (2 20 - 1) = 891289 (decimal) = 1101 1001 1001 1001 1001 see table 14 for integer and fractional divider ratios for 802.11g/b systems using a 20mhz comparison frequency. table 12. integer divider register (a3:a0 = 0011) bit recommended description d13:d8 000000 6 lsbs of 20-bit fractional portion of main divider d7:d0 01111001 8-bit integer portion of main divider. programmable from 64 to 255. table 13. fractional divider register (a3:a0 = 0100) bit recommended description d13:d0 11011001100110 14 msbs of 20-bit fractional portion of main divider 24 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch crystal oscillator the crystal oscillator has been optimized to work withlow-cost crystals (e.g., kyocera cx-3225sb). see figure 2. the crystal oscillator frequency can be fine tuned through bits d6:d0 in register 14 (a3:a0 = 1110), which control the value of c tune from 0.5pf to 15.4pf in 0.12pf steps. see the crystal-oscillator offsetfrequency vs. crystal-oscillator tuning bits graph in the typical operating characteristics . the crystal oscillator can be used as a buffer for an external reference fre-quency source. in this case, the reference signal is ac- coupled to the xtal pin, and capacitors c1 and c2 are not connected. when used as a buffer, the xtal input pin has to be ac-coupled. the xtal pin has an input impedance of 5k ? || 4pf, (set d6:d0 = 0000000 in register 14 a3:a0 = 1110). reference clock output divider/buffer the reference oscillator of the max2830 has a dividerand a buffered output for routing the reference clock to the accompanying baseband ic. bit d10 in register 14 (a3:a0 = 1110) sets the buffer divider to divide by 1 or 2, independent of the divide ratio for the reference fre- quency provided to the pll. bit b9 in the same register enables or disables the reference buffer output. see the clock output waveform in the typical operating characteristics . loop filter the pll charge-pump output, cpout (pin 24), con-nects to an external third-order, lowpass rc loop-filter, which in turn connects to the voltage tuning input, tune (pin 32), of the vco, completing the pll loop. the charge-pump output sink and source current is 1ma, and the vco tuning gain is 103mhz/v at 0.5v tune voltage and 86mhz/v at 2.2v tune voltage. the rc loop-filter values have been optimized for a loop band- width of 150khz, to achieve the desired rx/tx turn- around settling time, while maintaining loop stability and good phase noise. refer to the max2830 ev kit schematic for the recommended loop-filter component values. keep the line from this pin to the tune input as short as possible to prevent spurious pickup. lock-detector output the pll features a logic lock-detect output. a logic-highindicates the pll is locked, and a logic-low indicates the pll is not locked. bit d5 in register 5 (a3:a0 = 0101) enables or disables the lock-detect output. bit figure 2. crystal oscillator schematic xtal ctune 5.9k c tune c2 c1 for external reference clock set, c1 = c2 = open 1.35k 2829 max2830 table 14. ieee 802.11g/b divider-ratio programming words integer divider fractional divider f rf (mhz) (f rf / f comp ) a3:a0 = 0011, d7:d0 a3:a0 = 0100, d13:d0 a3:a0 = 0011, d13:d8 2412 120.6 0111 1000b 2666h 1ah 2417 120.85 0111 1000b 3666h 1ah 2422 121.1 0111 1001b 0666h 1ah 2427 121.35 0111 1001b 1666h 1ah 2432 121.6 0111 1001b 2666h 1ah 2437 121.85 0111 1001b 3666h 1ah 2442 122.1 0111 1010b 0666h 1ah 2447 122.35 0111 1010b 1666h 1ah 2452 122.6 0111 1010b 2666h 1ah 2457 122.85 0111 1010b 3666h 1ah 2462 123.1 0111 1011b 0666h 1ah 2467 123.35 0111 1011b 1666h 1ah 2472 123.6 0111 1011b 2666h 1ah 2484 124.2 0111 1100b 0ccch 33h maxim integrated 25 max2830 downloaded from: http:///
* the power-on register settings are not production tested. recommended register settings must be loaded after v cc is supplied. table 15. recommended register settings* data address register d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (a3:a0) table 0 01011101000000 0000 15 1 01000110011010 0001 16 2 01000000000011 0010 17 3 00000001111001 0011 18 4 11011001100110 0100 19 5 00000010100100 0101 20 6 00000001100000 0110 21 7 01000000100010 0111 22 8 10000000100001 1000 23 9 00001110110101 1001 24 1 0 01110110100100 1010 25 1 1 00000001111111 1011 26 1 2 00000101000000 1100 27 1 3 00111010010010 1101 28 1 4 00001100111011 1110 29 1 5 00000101000101 1111 30 bit 16 bit 2 bit 1 bit 24 bit 23 bit 15 t ch din t css sclk t cso t ds t dh t cl t csw t csh t cs1 cs figure 3. 3-wire spi serial-interface timing diagram d12 in register 1 (a3:a0 = 0001) configures the lock-detect output as a cmos or open-drain output. in open- drain output mode, bit d9 in register 5 (a3:a0 = 0101) enables or disables an internal 30k ? pullup resistor from the open-drain output. programmable registers and 3-wire spi-interface the max2830 includes 16 programmable, 18-bit reg-isters. the 14 most significant bits (msbs) are used for register data. the 4 least significant bits (lsbs) of each register contain the register address. see table 15 for a summary of the registers and recommended register settings. register data is loaded through the 3-wire spi/microwire-compatible serial interface. data is shifted in msb first and is framed by cs . when cs is low, the clock is active, and data is shifted with the ris-ing edge of the clock. when cs transitions high, the shift register is latched into the register selected by the contents of the address bits. see figure 3. only the last 18 bits shifted into the device are retained in the shift register. no check is made on the number of clock pulses. for programming data words less than 14 bits long, only the required data bits and the address bits need to be shifted, resulting in faster rx and tx gain control where only the lsbs need to be programmed. microwire is a trademark of national semiconductor corp. 26 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch table 21. register 5 (a3:a0 = 0101) bit recommended description d13:d10 0000 set to recommended value. d9 0 lock-detect output internal pullup resistor enable. set to 1 to enable internal 30k pullup resistor or set to 0 to disable the resistor. only available when lock-detect, open-drain outputis selected (a3:a0 = 0001, d12 = 1). d8:d6 010 set to recommended value. d5 1 lock-detect output enable. set to 1 to enable the lock-detect output or set to 0 to disable theoutput. the output is high impedance when disabled. d4:d3 00 set to recommended value. d2 1 reference frequency divider ratio to pll. set to 0 to divide by 1. set to 1 to divide by 2. d1:d0 00 set to recommended value. table 16. register 0 (a3:a0 = 0000) data bits recommended description d13:d11 000 set to recommended value. d10 1 fractional-n pll mode enable. set 1 to enable the fractional-n pll or set 0 to enable theinteger-n pll. d9:d0 1101000000 set to recommended value. table 17. register 1 (a3:a0 = 0001) data bits recommended description d13 0 set to recommended value. d12 1 lock-detector output select. set to 1 for cmos output. set to 0 for open-drain output. bit d9in register (a3:a0 = 0101) enables or disables an internal 30k pullup resistor in open-drain output mode. d11:d0 000110011010 set to recommended value. table 18. register 2 (a3:a0 = 0010) data bits recommended description d13:d0 01000000000011 set to recommended value. this register contains the 8-bit integer portion and 6 lsbs of the fractional portion of the divider ratio of the synthesizer. table 19. register 3 (a3:a0 = 0011) bit recommended description d13:d8 00000 6 lsbs of 20-bit fractional portion of main divider d7:d0 01111001 8-bit integer portion of main divider. programmable from 64 to 255. table 20. register 4 (a3:a0 = 0100) bit recommended description d13:d0 11011001100110 14 msbs of 20-bit fractional portion of main divider maxim integrated 27 max2830 downloaded from: http:///
table 22. register 6 (a3:a0 = 0110) data bit recommended description d13 0 set to recommended value. d12:d11 00 tx i/q calibration lo leakage and sideband detector gain-control bits. d12:d11 = 00: 9db;01 19db; 10: 29db; 11: 39db. d10:d7 0000 set to recommended value. d6 1 power-detector enable in tx mode. set to 1 to enable the power detector or set to 0 todisable the detector. d5:d2 1000 set to recommended value. d1 0 tx calibration mode. set to 1 to place the device in tx calibration mode or 0 to place the device in normal tx mode when rxtx is set to 1 (see table 32). d0 0 rx calibration mode. set to 1 to place the device in rx calibration mode or 0 to place thedevice in normal rx mode when rxtx is set to 0 (see table 32). table 23. register 7 (a3:a0 = 0111) bit recommended description d13:d12 01 receiver highpass corner frequency setting for rxhp = 0. set to 00 for 100hz, x1 for 4khz,and 10 for 30khz. d11:d6 000000 set to recommended value. d5:d3 100 transmitter lowpass filter corner frequency fine adjustment (relative to coarse setting).see table 9. bits d1:d0 in a3:a0 = 1000 provide the lowpass filter corner coarse adjustment. d2:d0 010 receiver lowpass filter corner frequency fine adjustment (relative to coarse setting). seetable 6. bits d1:d0 in a3:a0 = 1000 provide the lowpass filter corner coarse adjustment. table 24. register 8 (a3:a0 = 1000) bit recommended description d13 1 set to recommended value. d12 0 enable receiver gain programming through the serial interface. set to 1 to enable programming through the 3-wire serial interface (d6:d0 in register a3:a0 = 1011). set to 0 to enable programming in parallel through external digital pins (b7:b1). d11 0 set to recommended value. d10 0 rssi operating mode. set to 1 to enable rssi output independent of rxhp. set to 0 todisable rssi output if rxhp = 0, and enable the rssi output if rxhp = 1. d9:d8 00 rs s i, p ow er d etector , or tem p er atur e s ensor o utp ut s el ect. s et to 00 to enab l e the rs s i outp ut i n r ecei ve m od e. s et to 01 to enab l e the tem p er atur e sensor outp ut i n r ecei ve and tr ansm i t m od es. s et to 10 to enab l e the p ow er - d etector outp ut i n tr ansm i t m od e. s ee tab l e 7. d7:d2 001000 set to recommended value. d1:d0 01 receiver and transmitter lowpass filter corner frequency coarse adjustment. see tables 4and 7. 28 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch table 27. register 11 (a3:a0 = 1011) bit recommended description d13:d7 0000000 set to recommended value. d6:d5 11 lna gain control. set to 11 for high-gain mode. set to 10 for medium-gain mode, reducinglna gain by 16db. set to 0x for low-gain mode, reducing lna gain by 33db. d4:d0 11111 receiver vga control. set d4:d0 = 00000 for minimum gain and d4:d0 = 11111 formaximum gain. table 28. register 12 (a3:a0 = 1100) bit recommended description d13:d6 00000101 set to recommended value. d5:d0 000000 transmitter vga gain control. set d5:d0 = 000000 for minimum gain, and set d5:d0 =111111 for maximum gain. table 29. register 13 (a3:a0 = 1101) bit recommended description d13:d10 0011 set to recommended value. d9:d6 1010 set to recommended value. d5:d0 010010 set to recommended value. table 26. register 10 (a3:a0 = 1010) bit recommended description d13:d10 0111 p ow er - am p l i fi er e nab l e d el ay. s ets a d el ay b etw een rx tx l ow - to- hi g h tr ansi ti on and i nter nal p a enab l e. p r og r am m ab l e i n 0.5s step s. d 13:d 10 = 0001 ( 0.2?) and d 13:d 10 = 1111 ( 7?) . d9:d7 011 set to recommended value. d6:d3 0100 second-stage power-amplifier bias current adjustment. set to xxxx for 802.11g/b. d2:d0 100 first-stage power-amplifier bias current adjustment. set to xxx for 802.11g/b. table 25. register 9 (a3:a0 = 1001) bit recommended description d13:d11 000 set to recommended value. d10 0 enable transmitter gain programming through the serial or parallel interface. set to 1 toenable programming through the 3-wire serial interface (d5:d0 in register a3:a0 = 1011). set to 0 to enable programming in parallel through external digital pins (b6:b1). d9:d0 1110110101 set to recommended value. maxim integrated 29 max2830 downloaded from: http:///
modes of operation the modes of operation for the max2830 are shutdown,standby, transmit, receive, transmitter calibration, and receiver calibration. see table 32 for a summary of the modes of operation. the logic-input pins, shdn (pin 12) and rxtx (pin 48), control the various modes. shutdown mode the max2830 features a low-power shutdown modethat disables all circuit blocks, except the serial-inter- face and internal registers, allowing the registers to be loaded and values maintained, as long as v cc is applied. set shdn and rxtx logic-low to place the device in shutdown mode. after a supply voltage rampup, supply current in shutdown mode could be high. program the default value to spi register 0 to eliminate high shutdown current. standby mode the standby mode is used to enable the frequency syn-thesizer block while the rest of the device is powered down. in this mode, the pll, vco, and lo generators table 30. register 14 (a3:a0 = 1110) bit recommended description d13:d11 000 set to recommended value. d10 0 reference clock output divider ratio. set 1 to divide by 2 or set 0 to divide by 1. d9 1 refer ence c l ock outp ut e nab l e. s et 1 to enab l e the r efer ence cl ock outp ut or set 0 to d i sab l e. d8:d7 10 set to recommended value. d6:d0 xxxxxxx crystal-oscillator fine tune. tunes crystal oscillator over ?0ppm to within ?ppm. table 31. register 15 (a3:a0 = 1111) bit recommended description d13:d12 00 set to recommended value. d11:d10 00 receiver i/q output common-mode voltage adjustment. set d11:d10 = 00: 1.1v, 01: 1.2v, 10: 1.3v, 11: 1.45v. d9:d0 0101000101 set to recommended value. table 32. operating mode table logic pins register settings circuit block states mode shdn rxtx d1:d0 (a3:a0 = 0110) rx path tx path pll, vco, lo gen, autotuner calibrationsections on shutdown 0 0 00 off off off none standby 0 1 00 off off on none rx 1 0 x0 on off on none tx 1 1 0x off on on none rx calibration 1 0 x1 on (except lna) upconverters on cal tone, rf phase shift, tx filter tx calibration 1 1 1x off on (except pa driver and pa) on am detector, rx i/q buffers x = don? care. note: see table 1 for rx/tx and antenna diversity operating mode. x = don? care. 30 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch are on, so that tx or rx modes can be quickly enabledfrom this mode. set shdn to a logic-low and rxtx to a logic-high to place the device in standby mode. receive (rx) mode the complete receive signal path is enabled in thismode. set shdn to logic-high and rxtx to logic-low to place the device in rx mode. transmit (tx) mode the complete transmitter signal path is enabled in thismode. set shdn and rxtx to logic-high to place the device in tx mode. rx/tx calibration mode the max2830 features rx/tx calibration modes to detecti/q imbalances and transmit lo leakage. in the tx cali- bration mode, all tx circuit blocks, except the pa driver and external pa, are powered on and active. the am detector and receiver i and q channel buffers are also on, along with multiplexers in the receiver side to route this am detector? signal. in this mode, the lo leakage calibration is done only for the lo leakage signal that is present at the center frequency of the channel (i.e., in the middle of the ofdm or qpsk spectrum). the lo leakage calibration includes the effect of all dc offsets in the entire baseband paths of the i/q modulator and direct leakage of the lo to the i/q modulator output. the lo leakage and sideband detector output are taken at the receiver i and q channel outputs during this calibration phase.during tx lo leakage and i/q imbalance calibration, a sine and cosine signal (f = f tone ) is input to the base- band i/q tx pins from the baseband ic. at the lo leak-age and sideband-detector output, the lo leakage corresponds to the signal at f tone and the sideband suppression corresponds to the signal at 2 x f tone . the output power of these signals vary 1db for 1db of vari-ation in the lo leakage and sideband suppression. to calibrate the tx path, first set the power-detector gain to 9db using d12:d11 in register 6 (see table 22). adjust the dc offset of the baseband inputs to mini- mize the signal at f tone (lo leakage). then, adjust the baseband input relative magnitude and phase offsetsto reduce the signal at 2 x f tone . in rx calibration mode, the calibrated tx rf signal isinternally routed to the rx inputs. in this mode, the vco/lo generator/pll blocks are powered on and active except for the low-noise amplifier (lna). applications information layout issues the max2830 ev kit can be used as a starting point forlayout. for best performance, take into consideration grounding and rf, baseband, and power-supply routing. make connections from vias to the ground plane as short as possible. do not connect the device ground pin to the exposed paddle ground. keep the buffered clock output trace as short as possible. do not share the trace with the rf input layer, especially on or interlayer or back side of the board. on the high-impedance ports, keep traces short to minimize shunt capacitance. ev kit gerber files can be requested at www.maxim-ic.com. power-supply layout to minimize coupling between different sections of theic, a star power-supply routing configuration with a large decoupling capacitor at a central v cc node is recommended. the v cc traces branch out from this node, each going to a separate v cc node in the circuit. place a bypass capacitor as close as possible to each supply pin. this arrangement provides local decouplingat each v cc pin. use at least one via per bypass capacitor for a low-inductance ground connection. donot share the capacitor ground vias with any other branch and the exposed paddle ground. maxim integrated 31 max2830 downloaded from: http:///
sclk power supply on i ref shutdown mode standby mode din shutdownsclk (clock) din (data) rxtx receive mode transmit mode internal pa enabled pa enable (drives power ramp control) 3-wire serial interface available power spi: channel frequency, pa bias, transmitter linearity, receiver rssi operation, calibration mode, etc. mac spi mac 0 to 7 s cs shdn cs (select) max2830 figure 4. timing diagram pin configuration top view max2830 gndcp ep* *exposed paddle shdn b2 ant2- ant2+ b3 v ccpa b7 ant1- ant1+ b6 + gndrxlna v cclna cpout b1 ld clockout v ccpll din sclk v cctxmx rssi cs b5 v cctxpa rxbbi- rxbbi+ v ccrxvga rxhp v ccrxfl txbbq- txbbq+ txbbi- txbbi+ v ccrxmx antsel rxtx 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 3635 34 33 32 31 30 29 28 27 26 25 rxbbq+rxbbq- b4 bypass tune gndvco v ccvco ctune xtal v ccxtal v cccp thin qfn chip information process: bicmos package information for the latest package outline information and land patterns(footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only.package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 48 tqfn-ep t4877+4 21-0144 90-0130 32 maxim integrated 2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch max2830 downloaded from: http:///
2.4ghz to 2.5ghz 802.11g/b rf transceiver, pa, and rx/tx/antenna diversity switch revision history revision number revision date description pages changed 0 3/07 initial release 1 7/09 corrected table 12 24 2 3/11 corrected conditions for rx i/q output common-mode voltage variation in the dc electrical characteristics ; corrected tables 15 and 31; added text to shutdown mode section 2, 26, 30 max2830 downloaded from: http:/// 0d[lp,qwhjudwhg5lr5reohv6dq-rvh&$86$ maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. ? maxim integrated the maxim logo and maxim integrated are trademarks of maxim integrated products, inc.

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